A prior art method of forming a board-on-chip package (which can be generally referred to as a die package) is described with reference to FIGS. 1-5. Referring first to FIG. 1, such illustrates a fragment of an assembly 10 comprising an insulative material substrate 12. Substrate 12 can comprise, for example, a circuit board.
Substrate 12 comprises a top surface 13 and slits 18 extending therethrough. Circuitry 16 is formed on top of surface 13. Circuitry 16 and slits 18 form repeating patterns across top surface 13. The repeating patterns define separate units 19, 21 and 23, each of which ultimately forms a separate board-on-chip package.
Referring to FIGS. 2-4, an enlarged segment of substrate 12, corresponding to unit 21, is shown in three different views. FIG. 2 is a top view similar to the view of FIG. 1, FIG. 3 is view along the line 3--3 of FIG. 2, and FIG. 4 is a view along the line 4--4 of FIG. 3. Substrate 12 is inverted in the view of FIG. 3 relative to the view of FIGS. 1 and 2. Accordingly, surface 13 (referred to as a top surface in referring to FIGS. 1 and 2) is a bottom surface in the view of FIG. 3. In referring to FIG. 3, surface 13 will be referred to as a first surface.
Substrate 12 comprises a second surface 15 in opposing relation relative to first surface 13. A semiconductive material-comprising chip (or die) 14 is adhered to surface 15 via a pair of adhesive strips 20. Strips 20 can comprise, for example, tape having a pair of opposing surfaces 22 and 24, with adhesive being provided on both of such opposing surfaces. Strips 20 typically comprise insulative material. Wire bonds 28 (only some of which are labeled in FIG. 2) extend from circuitry 16 and through slit 18 to electrically connect circuitry 16 to bonding pads 25 (only some of which are labeled in FIG. 2) associated with chip 14, and to accordingly electrically connect circuitry 16 with circuitry (not shown) comprised by chip 14. Chip 14 comprises a surface 17 which faces surface 15 of substrate 12. The bonding pads are on surface 17. (The wire bonds and bonding pads are not shown in FIG. 4 for purposes of clarity in the illustration.)
FIG. 5 illustrates further processing of the assembly 10. Specifically, FIG. 5 illustrates units 19 and 21 of FIG. 1 after a first encapsulant 40 is provided over wire bonds 28, and a second encapsulant 42 is provided over chips 14 associated with units 19 and 21. First and second encapsulants 40 and 42 can comprise the same material and typically comprise an insulative material, such as, for example, cured epoxy.
Conductive balls 31 are formed over portions of circuitry 16 (shown in FIGS. 1 and 2) to form a ball grid array over circuitry 16. Such array can subsequently be utilized to form a plurality of interconnects from circuitry 16 to other circuitry (not shown). Conductive balls 31 can be formed of, for example, tin, copper or gold.
Substrate 12 is subjected to a singulation process which separates units 19 and 21 from one another, and thus forms individual board-on-chip packages from units 19 and 21. The singulation process can include, for example, cutting through encapsulant 42 and substrate 12.
Difficulties can occur in the formation of the wire bonds associated with a board-chip-package. Among the methods commonly utilized for forming such wire bonds are a TESSERA.TM. process and a so-called tab bonding process. In either of such processes, the wires utilized for wire-bonding initially have one end bonded to circuitry 16. The wires are provided to extend at least partially across slit 18 so that a second end (which is not bonded to circuitry 16) extends over or past slit 18. A rod is then utilized to individually and sequentially push each wire into slit 18 and to hold the wire against chip 14 during an ultrasonic welding process. The ultrasonic welding individually and sequentially adheres the second end of each wire to a bonding pad 25.
It would be desirable to develop alternative methods for forming wire bonds.